This work discusses memory-immersed collaborative digitization among
compute-in-memory (CiM) arrays to minimize the area overheads of a conventional
analog-to-digital converter (ADC) for deep learning inference. Thereby, using
the proposed scheme, significantly more CiM arrays can be accommodated within
limited footprint designs to improve parallelism and minimize external memory
accesses. Under the digitization scheme, CiM arrays exploit their parasitic bit
lines to form a within-memory capacitive digital-to-analog converter (DAC) that
facilitates area-efficient successive approximation (SA) digitization. CiM
arrays collaborate where a proximal array digitizes the analog-domain
product-sums when an array computes the scalar product of input and weights. We
discuss various networking configurations among CiM arrays where Flash, SA, and
their hybrid digitization steps can be efficiently implemented using the
proposed memory-immersed scheme. The results are demonstrated using a 65 nm
CMOS test chip. Compared to a 40 nm-node 5-bit SAR ADC, our 65 nm design
requires $\sim$25$\times$ less area and $\sim$1.4$\times$ less energy by
leveraging in-memory computing structures. Compared to a 40 nm-node 5-bit Flash
ADC, our design requires $\sim$51$\times$ less area and $\sim$13$\times$ less
energy.

利用 memory-immersed 方案，在有限的面积内，减少 ADC 硬件开销，提高并行性能和减少外部内存访问。