Neural decoders for quantum error correction (QEC) rely on neural networks to
classify syndromes extracted from error correction codes and find appropriate
recovery operators to protect logical information against errors. Despite the
good performance of neural decoders, important practical requirements remain to
be achieved, such as minimizing the decoding time to meet typical rates of
syndrome generation in repeated error correction schemes, and ensuring the
scalability of the decoding approach as the code distance increases. Designing
a dedicated integrated circuit to perform the decoding task in co-integration
with a quantum processor appears necessary to reach these decoding time and
scalability requirements, as routing signals in and out of a cryogenic
environment to be processed externally leads to unnecessary delays and an
eventual wiring bottleneck. In this work, we report the design and performance
analysis of a neural decoder inference accelerator based on an in-memory
computing (IMC) architecture, where crossbar arrays of resistive memory devices
are employed to both store the synaptic weights of the decoder neural network
and perform analog matrix-vector multiplications during inference. In
proof-of-concept numerical experiments supported by experimental measurements,
we investigate the impact of TiO$_\textrm{x}$-based memristive devices'
non-idealities on decoding accuracy. Hardware-aware training methods are
developed to mitigate the loss in accuracy, allowing the memristive neural
decoders to achieve a pseudo-threshold of $9.23\times 10^{-4}$ for the
distance-three surface code, whereas the equivalent digital neural decoder
achieves a pseudo-threshold of $1.01\times 10^{-3}$. This work provides a
pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated
QEC.

基于内存计算的神经解码器推理加速器在量子纠错中的设计和性能分析，以解决解码时间和可扩展性要求，研究了非理想性对解码准确性的影响，为集成的量子纠错提供了可扩展，快速和低功耗的低温内存计算硬件。

一种低温记忆电阻神经解码器用于容错量子错误校正

A Cryogenic Memristive Neural Decoder for Fault-tolerant Quantum Error  Correction

In-memory computing is a promising non-von Neumann approach for making
energy-efficient deep learning inference hardware. Crossbar arrays of resistive
memory devices can be used to encode the network weights and perform efficient
analog matrix-vector multiplications without intermediate movements of data.
However, due to device variability and noise, the network needs to be trained
in a specific way so that transferring the digitally trained weights to the
analog resistive memory devices will not result in significant loss of
accuracy. Here, we introduce a methodology to train ResNet-type convolutional
neural networks that results in no appreciable accuracy loss when transferring
weights to in-memory computing hardware based on phase-change memory (PCM). We
also propose a compensation technique that exploits the batch normalization
parameters to improve the accuracy retention over time. We achieve a
classification accuracy of 93.7% on the CIFAR-10 dataset and a top-1 accuracy
on the ImageNet benchmark of 71.6% after mapping the trained weights to PCM.
Our hardware results on CIFAR-10 with ResNet-32 demonstrate an accuracy above
93.5% retained over a one day period, where each of the 361,722 synaptic
weights of the network is programmed on just two PCM devices organized in a
differential configuration.

介绍了一种在内存计算硬件上训练 ResNet 类型卷积神经网络的方法，并提出了一种基于批标准化参数的补偿技术，可以在映射到 PCM 后实现分类精度高达 93.7％ 的 CIFAR-10 数据集和 71.6％ 的 ImageNet 基准测试的 top-1 精度。