Systolic array has emerged as a prominent architecture for Deep Neural
Network (DNN) hardware accelerators, providing high-throughput and low-latency
performance essential for deploying DNNs across diverse applications. However,
when used in safety-critical applications, reliability assessment is mandatory
to guarantee the correct behavior of DNN accelerators. While fault injection
stands out as a well-established practical and robust method for reliability
assessment, it is still a very time-consuming process. This paper addresses the
time efficiency issue by introducing a novel hierarchical software-based
hardware-aware fault injection strategy tailored for systolic array-based DNN
accelerators.

为 Systolic 阵列硬件加速器引入了一种新的层次化基于软件的硬件感知的故障注入策略，以解决可靠性评估的时间效率问题。

SAFFIRA: 用于评估基于 Systolic-Array 的 DNN 加速器可靠性的框架

SAFFIRA: a Framework for Assessing the Reliability of  Systolic-Array-Based DNN Accelerators

Recurrent neural networks such as Long Short-Term Memories (LSTMs) learn
temporal dependencies by keeping an internal state, making them ideal for
time-series problems such as speech recognition. However, the output-to-input
feedback creates distinctive memory bandwidth and scalability challenges in
designing accelerators for RNNs. We present Muntaniala, an RNN accelerator
architecture for LSTM inference with a silicon-measured energy-efficiency of
3.25$TOP/s/W$ and performance of 30.53$GOP/s$ in UMC 65 $nm$ technology. The
scalable design of Muntaniala allows running large RNN models by combining
multiple tiles in a systolic array. We keep all parameters stationary on every
die in the array, drastically reducing the I/O communication to only loading
new features and sharing partial results with other dies. For quantifying the
overall system power, including I/O power, we built Vau da Muntanialas, to the
best of our knowledge, the first demonstration of a systolic multi-chip-on-PCB
array of RNN accelerator. Our multi-die prototype performs LSTM inference with
192 hidden states in 330$\mu s$ with a total system power of 9.0$mW$ at 10$MHz$
consuming 2.95$\mu J$. Targeting the 8/16-bit quantization implemented in
Muntaniala, we show a phoneme error rate (PER) drop of approximately 3% with
respect to floating-point (FP) on a 3L-384NH-123NI LSTM network on the TIMIT
dataset.

利用 Muntaniala 架构为 LSTM 推理提供 RNN 加速器，实现了 3.25$TOP/s/W$ 的芯片测量能效和 30.53$GOP/s$ 的性能。

Vau da muntanialas: RNN 推断的能效多芯片可扩展加速

Vau da muntanialas: Energy-efficient multi-die scalable acceleration of RNN inference

Graph Convolutional Networks (GCNs) have emerged as the state-of-the-art deep
learning model for representation learning on graphs. It is challenging to
accelerate training of GCNs, due to (1) substantial and irregular data
communication to propagate information within the graph, and (2) intensive
computation to propagate information along the neural network layers. To
address these challenges, we design a novel accelerator for training GCNs on
CPU-FPGA heterogeneous systems, by incorporating multiple
algorithm-architecture co-optimizations. We first analyze the computation and
communication characteristics of various GCN training algorithms, and select a
subgraph-based algorithm that is well suited for hardware execution. To
optimize the feature propagation within subgraphs, we propose a lightweight
pre-processing step based on a graph theoretic approach. Such pre-processing
performed on the CPU significantly reduces the memory access requirements and
the computation to be performed on the FPGA. To accelerate the weight update in
GCN layers, we propose a systolic array based design for efficient
parallelization. We integrate the above optimizations into a complete hardware
pipeline, and analyze its load-balance and resource utilization by accurate
performance modeling. We evaluate our design on a Xilinx Alveo U200 board
hosted by a 40-core Xeon server. On three large graphs, we achieve an order of
magnitude training speedup with negligible accuracy loss, compared with
state-of-the-art implementation on a multi-core platform.

通过 CPU-FPGA 异构系统，我们设计了一种新型加速器，通过算法 - 架构协同优化，提升 Graph Convolutional Networks 训练的速度。我们采用子图算法，优化特征传播，并提出基于 systolic array 的设计，实现了如此高效的加速。在 Xilinx Alveo U200 及 40 核 Xeon 服务器上，我们的设计比现有多核平台的最新实现快一个数量级，且几乎没有精度损失。