Systolic arrays are a prominent choice for deep neural network (DNN)
accelerators because they offer parallelism and efficient data reuse. Improving
the reliability of DNN accelerators is crucial as hardware faults can degrade
the accuracy of DNN inferencing. Systolic arrays make use of a large number of
processing elements (PEs) for parallel processing, but when one PE is faulty,
the error propagates and affects the outcomes of downstream PEs. Due to the
large number of PEs, the cost associated with implementing hardware-based
runtime monitoring of every single PE is infeasible. We present a solution to
optimize the placement of hardware monitors within systolic arrays. We first
prove that $2N-1$ monitors are needed to localize a single faulty PE and we
also derive the monitor placement. We show that a second placement optimization
problem, which minimizes the set of candidate faulty PEs for a given number of
monitors, is NP-hard. Therefore, we propose a heuristic approach to balance the
reliability and hardware resource utilization in DNN accelerators when number
of monitors is limited. Experimental evaluation shows that to localize a single
faulty PE, an area overhead of only 0.33% is incurred for a $256\times 256$
systolic array.

为提高深度神经网络加速器的可靠性，本研究在 systolic arrays 中优化硬件监控器的放置，以平衡可靠性和硬件资源利用。实验评估结果显示，在 $256	imes 256$ 的 systolic array 中，定位一个故障的 PE 仅带来 0.33% 的面积开销。

深度神经网络加速器故障定位的监视器部署

Monitor Placement for Fault Localization in Deep Neural Network  Accelerators

Systolic Arrays are one of the most popular compute substrates within Deep
Learning accelerators today, as they provide extremely high efficiency for
running dense matrix multiplications. However, the research community lacks
tools to insights on both the design trade-offs and efficient mapping
strategies for systolic-array based accelerators. We introduce Systolic CNN
Accelerator Simulator (SCALE-Sim), which is a configurable systolic array based
cycle accurate DNN accelerator simulator. SCALE-Sim exposes various
micro-architectural features as well as system integration parameters to the
designer to enable comprehensive design space exploration. This is the first
systolic-array simulator tuned for running DNNs to the best of our knowledge.
Using SCALE-Sim, we conduct a suite of case studies and demonstrate the effect
of bandwidth, data flow and aspect ratio on the overall runtime and energy of
Deep Learning kernels across vision, speech, text, and games. We believe that
these insights will be highly beneficial to architects and ML practitioners.

本研究介绍了一种基于可配置的 Systolic 数组的 DNN 加速器模拟器 ——SCALE-Sim，并使用其对视觉、语音、文本和游戏等领域的深度学习内核进行了一系列案例研究，证明了带宽、数据流和纵横比对整体运行时间和能耗的影响，为架构师和 ML 从业者提供了有价值的见解。