Recently, there has been a surging interest in using large language models
(LLMs) for Verilog code generation. However, the existing approaches are
limited in terms of the quality of the generated Verilog code. To address such
limitations, this paper introduces an innovative multi-expert LLM architecture
for Verilog code generation (MEV-LLM). Our architecture uniquely integrates
multiple LLMs, each specifically fine-tuned with a dataset that is categorized
with respect to a distinct level of design complexity. It allows more targeted
learning, directly addressing the nuances of generating Verilog code for each
category. Empirical evidence from experiments highlights notable improvements
in terms of the percentage of generated Verilog outputs that are syntactically
and functionally correct. These findings underscore the efficacy of our
approach, promising a forward leap in the field of automated hardware design
through machine learning.

最近，使用大型语言模型 (LLMs) 进行 Verilog 代码生成引起了人们的极大兴趣。然而，现有的方法在生成的 Verilog 代码质量方面存在一定的局限性。为了解决这些限制，本文介绍了一种创新的基于多专家的 LLM 架构用于 Verilog 代码生成 (MEV-LLM)。我们的架构独特地集成了多个 LLMs，每个都经过特定的微调，与一个按设计复杂度分级的数据集相对应。它允许更有针对性地学习，直接解决每个类别的 Verilog 代码生成的细微差别。实验证据突出了在句法和功能正确的生成的 Verilog 输出百分比方面的显著改进。这些发现强调了我们方法的效力，在通过机器学习实现自动硬件设计领域中有了一个飞跃。

一个用于 Verilog 代码生成的多专家大型语言模型架构

A Multi-Expert Large Language Model Architecture for Verilog Code  Generation

Despite the growing interest in ML-guided EDA tools from RTL to GDSII, there
are no standard datasets or prototypical learning tasks defined for the EDA
problem domain. Experience from the computer vision community suggests that
such datasets are crucial to spur further progress in ML for EDA. Here we
describe our experience curating two large-scale, high-quality datasets for
Verilog code generation and logic synthesis. The first, VeriGen, is a dataset
of Verilog code collected from GitHub and Verilog textbooks. The second,
OpenABC-D, is a large-scale, labeled dataset designed to aid ML for logic
synthesis tasks. The dataset consists of 870,000 And-Inverter-Graphs (AIGs)
produced from 1500 synthesis runs on a large number of open-source hardware
projects. In this paper we will discuss challenges in curating, maintaining and
growing the size and scale of these datasets. We will also touch upon questions
of dataset quality and security, and the use of novel data augmentation tools
that are tailored for the hardware domain.

描述了在硬件域中策划、维护和扩大两个大规模、高质量数据集的挑战，以及有关数据集质量、安全性和硬件领域定制数据增强工具的使用的相关问题。

走向 ML4EDA 的 Imagenets

Towards the Imagenets of ML4EDA

The increasing popularity of large language models (LLMs) has paved the way
for their application in diverse domains. This paper proposes a benchmarking
framework tailored specifically for evaluating LLM performance in the context
of Verilog code generation for hardware design and verification. We present a
comprehensive evaluation dataset consisting of 156 problems from the Verilog
instructional website HDLBits. The evaluation set consists of a diverse set of
Verilog code generation tasks, ranging from simple combinational circuits to
complex finite state machines. The Verilog code completions can be
automatically tested for functional correctness by comparing the transient
simulation outputs of the generated design with a golden solution. We also
demonstrate that the Verilog code generation capability of pretrained language
models could be improved with supervised fine-tuning by bootstrapping with LLM
generated synthetic problem-code pairs.

该论文提出了一种专门为评估大型语言模型在硬件设计和验证中的 Verilog 代码生成性能而设计的基准测试框架，演示了预训练语言模型的 Verilog 代码生成能力可以通过使用 LLM 生成的合成问题 - 代码对进行监督微调来提高。