AI has led to significant advancements in computer vision and image
processing tasks, enabling a wide range of applications in real-life scenarios,
from autonomous vehicles to medical imaging. Many of those applications require
efficient object detection algorithms and complementary real-time, low latency
hardware to perform inference of these algorithms. The YOLO family of models is
considered the most efficient for object detection, having only a single model
pass. Despite this, the complexity and size of YOLO models can be too
computationally demanding for current edge-based platforms. To address this, we
present SATAY: a Streaming Architecture Toolflow for Accelerating YOLO. This
work tackles the challenges of deploying stateof-the-art object detection
models onto FPGA devices for ultralow latency applications, enabling real-time,
edge-based object detection. We employ a streaming architecture design for our
YOLO accelerators, implementing the complete model on-chip in a deeply
pipelined fashion. These accelerators are generated using an automated
toolflow, and can target a range of suitable FPGA devices. We introduce novel
hardware components to support the operations of YOLO models in a dataflow
manner, and off-chip memory buffering to address the limited on-chip memory
resources. Our toolflow is able to generate accelerator designs which
demonstrate competitive performance and energy characteristics to GPU devices,
and which outperform current state-of-the-art FPGA accelerators.

在这篇论文中，我们介绍了一种用于加速 YOLO 模型的流式体系结构工具流 SATAY，通过采用流式体系结构设计和引入新的硬件组件，以适应低延迟应用的需求，我们在 FPGA 设备上实现了实时的边缘物体检测，并展示了与 GPU 设备相比竞争性能和能源特性优势的加速器设计。

SATAY: 用于在 FPGA 设备上加速 YOLO 模型的流处理架构工具流

SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on  FPGA Devices

In this paper we have addressed the implementation of the accumulation and
projection of high-resolution event data stream (HD -1280 x 720 pixels) onto
the image plane in FPGA devices. The results confirm the feasibility of this
approach, but there are a number of challenges, limitations and trade-offs to
be considered. The required hardware resources of selected data
representations, such as binary frame, event frame, exponentially decaying time
surface and event frequency, were compared with those available on several
popular platforms from AMD Xilinx. The resulting event frames can be used for
typical vision algorithms, such as object classification and detection, using
both classical and deep neural network methods.

通过 FPGA 设备实现高分辨率事件数据流（HD-1280 x 720 像素）的累积与投影，研究探索了该方法的可行性、挑战、限制和权衡，并与 AMD Xilinx 等平台上的可用数据表示进行了比较。所得的事件帧可以用于经典和深度神经网络方法的目标分类与检测等视觉算法。

使用 SoC FPGA 设备生成高清事件帧

High-definition event frame generation using SoC FPGA devices

Surveillance systems, autonomous vehicles, human monitoring systems, and
video retrieval are just few of the many applications in which 3D Convolutional
Neural Networks are exploited. However, their extensive use is restricted by
their high computational and memory requirements, especially when integrated
into systems with limited resources. This study proposes a toolflow that
optimises the mapping of 3D CNN models for Human Action Recognition onto FPGA
devices, taking into account FPGA resources and off-chip memory
characteristics. The proposed system employs Synchronous Dataflow (SDF) graphs
to model the designs and introduces transformations to expand and explore the
design space, resulting in high-throughput designs. A variety of 3D CNN models
were evaluated using the proposed toolflow on multiple FPGA devices,
demonstrating its potential to deliver competitive performance compared to
earlier hand-tuned and model-specific designs.

研究提出一种工具流程，将 3D CNN 模型优化到 FPGA 设备上，采用同步数据流图来模拟设计并引入转换来拓展和探索设计空间，以实现高吞吐量设计。在多个 FPGA 设备上评估了各种 3D CNN 模型，证明了与早期手动调整和特定模型的设计相比，该工具流程具有竞争性的性能。