As Neural Processing Units (NPU) or accelerators are increasingly deployed in
a variety of applications including safety critical applications such as
autonomous vehicle, and medical imaging, it is critical to understand the
fault-tolerance nature of the NPUs. We present a reliability study of Arm's
Ethos-U55, an important industrial-scale NPU being utilised in embedded and IoT
applications. We perform large scale RTL-level fault injections to characterize
Ethos-U55 against the Automotive Safety Integrity Level D (ASIL-D) resiliency
standard commonly used for safety-critical applications such as autonomous
vehicles. We show that, under soft errors, all four configurations of the NPU
fall short of the required level of resiliency for a variety of neural networks
running on the NPU. We show that it is possible to meet the ASIL-D level
resiliency without resorting to conventional strategies like Dual Core Lock
Step (DCLS) that has an area overhead of 100%. We achieve so through selective
protection, where hardware structures are selectively protected (e.g.,
duplicated, hardened) based on their sensitivity to soft errors and their
silicon areas. To identify the optimal configuration that minimizes the area
overhead while meeting the ASIL-D standard, the main challenge is the large
search space associated with the time-consuming RTL simulation. To address this
challenge, we present a statistical analysis tool that is validated against Arm
silicon and that allows us to quickly navigate hundreds of billions of fault
sites without exhaustive RTL fault injections. We show that by carefully
duplicating a small fraction of the functional blocks and hardening the Flops
in other blocks meets the ASIL-D safety standard while introducing an area
overhead of only 38%.

通过大规模的 RTL 级故障注入以及选择性保护硬件结构，本研究对 Arm 的 Ethos-U55 进行可靠性研究，展示了满足 ASIL-D 安全标准的优化配置，并在仅增加 38% 面积开销的情况下实现安全性。

对 Arm Ethos-U55 嵌入式机器学习加速器软错误容忍性的表征

Characterizing Soft-Error Resiliency in Arm's Ethos-U55 Embedded Machine  Learning Accelerator

As the modern CPU, GPU, and NPU chip design complexity and transistor counts
keep increasing, and with the relentless shrinking of semiconductor technology
nodes to nearly 1 nanometer, the placement and routing have gradually become
the two most pivotal processes in modern very-large-scale-integrated (VLSI)
circuit back-end design. How to evaluate routability efficiently and accurately
in advance (at the placement and global routing stages) has grown into a
crucial research area in the field of artificial intelligence (AI) assisted
electronic design automation (EDA). In this paper, we propose a novel U-Net
variant model boosted by an Inception embedded module to predict Routing
Congestion (RC) and Design Rule Checking (DRC) hotspots. Experimental results
on the recently published CircuitNet dataset benchmark show that our proposed
method achieves up to 5% (RC) and 20% (DRC) rate reduction in terms of
Avg-NRMSE (Average Normalized Root Mean Square Error) compared to the classic
architecture. Furthermore, our approach consistently outperforms the prior
model on the SSIM (Structural Similarity Index Measure) metric.

我们提出了一种新的 U-Net 变体模型，通过嵌入 Inception 模块来预测路由阻塞和设计规则检查热点，实验证明我们的方法在 Avg-NRMSE 指标上比经典结构分别实现了 5%（RC）和 20%（DRC） 的准确率提升，并且在 SSIM 度量标准上始终优于之前的模型。

轻量级增强 Inception U-Net 神经网络用于布线可行性预测

A Lightweight Inception Boosted U-Net Neural Network for Routability  Prediction

The performance of mobile AI accelerators has been evolving rapidly in the
past two years, nearly doubling with each new generation of SoCs. The current
4th generation of mobile NPUs is already approaching the results of
CUDA-compatible Nvidia graphics cards presented not long ago, which together
with the increased capabilities of mobile deep learning frameworks makes it
possible to run complex and deep AI models on mobile devices. In this paper, we
evaluate the performance and compare the results of all chipsets from Qualcomm,
HiSilicon, Samsung, MediaTek and Unisoc that are providing hardware
acceleration for AI inference. We also discuss the recent changes in the
Android ML pipeline and provide an overview of the deployment of deep learning
models on mobile devices. All numerical results provided in this paper can be
found and are regularly updated on the official project website:
this http URL

本文评估了高通、海思、三星、联发科和紫光展锐提供的 AI 推理硬件加速的所有芯片组的性能，并比较了它们的结果。同时，我们还讨论了 Android ML 流水线的最近变化，并提供了在移动设备上部署深度学习模型的概述。