As the modern CPU, GPU, and NPU chip design complexity and transistor counts
keep increasing, and with the relentless shrinking of semiconductor technology
nodes to nearly 1 nanometer, the placement and routing have gradually become
the two most pivotal processes in modern very-large-scale-integrated (VLSI)
circuit back-end design. How to evaluate routability efficiently and accurately
in advance (at the placement and global routing stages) has grown into a
crucial research area in the field of artificial intelligence (AI) assisted
electronic design automation (EDA). In this paper, we propose a novel U-Net
variant model boosted by an Inception embedded module to predict Routing
Congestion (RC) and Design Rule Checking (DRC) hotspots. Experimental results
on the recently published CircuitNet dataset benchmark show that our proposed
method achieves up to 5% (RC) and 20% (DRC) rate reduction in terms of
Avg-NRMSE (Average Normalized Root Mean Square Error) compared to the classic
architecture. Furthermore, our approach consistently outperforms the prior
model on the SSIM (Structural Similarity Index Measure) metric.

我们提出了一种新的 U-Net 变体模型，通过嵌入 Inception 模块来预测路由阻塞和设计规则检查热点，实验证明我们的方法在 Avg-NRMSE 指标上比经典结构分别实现了 5%（RC）和 20%（DRC） 的准确率提升，并且在 SSIM 度量标准上始终优于之前的模型。

轻量级增强 Inception U-Net 神经网络用于布线可行性预测

A Lightweight Inception Boosted U-Net Neural Network for Routability  Prediction

The design automation of analog circuits is a longstanding challenge in the
integrated circuit field. This paper presents a deep reinforcement learning
method to expedite the design of analog circuits at the pre-layout stage, where
the goal is to find device parameters to fulfill desired circuit
specifications. Our approach is inspired by experienced human designers who
rely on domain knowledge of analog circuit design (e.g., circuit topology and
couplings between circuit specifications) to tackle the problem. Unlike all
prior methods, our method originally incorporates such key domain knowledge
into policy learning with a graph-based policy network, thereby best modeling
the relations between circuit parameters and design targets. Experimental
results on exemplary circuits show it achieves human-level design accuracy
(~99%) with 1.5x efficiency of existing best-performing methods. Our method
also shows better generalization ability to unseen specifications and
optimality in circuit performance optimization. Moreover, it applies to
designing diverse analog circuits across different semiconductor technologies,
breaking the limitations of prior ad-hoc methods in designing one particular
type of analog circuits with conventional semiconductor technology.

本研究介绍了基于深度强化学习、图模型策略网络和模拟电路设计领域知识的自动设计方法，以加快模拟电路的设计。该方法在电路参数和设计目标之间建立关系，实现了 99% 的设计准确率和 1.5 倍的效率提升，并支持不同半导体技术的模拟电路设计。