Large Language Models (LLMs) have demonstrated capabilities for producing
code in Hardware Description Languages (HDLs). However, most of the focus
remains on their abilities to write functional code, not test code. The
hardware design process consists of both design and test, and so eschewing
validation and verification leaves considerable potential benefit unexplored,
given that a design and test framework may allow for progress towards full
automation of the digital design pipeline. In this work, we perform one of the
first studies exploring how a LLM can both design and test hardware modules
from provided specifications. Using a suite of 8 representative benchmarks, we
examined the capabilities and limitations of the state-of-the-art
conversational LLMs when producing Verilog for functional and verification
purposes. We taped out the benchmarks on a Skywater 130nm shuttle and received
the functional chip.

该研究使用八个代表性基准测试探究了领先技术的对话式大型语言模型在功能和验证目的上生成 Verilog 的能力和限制。结果表明，大型语言模型在硬件模块的设计和测试中具有潜力，并可朝着全自动数字设计流程的进展迈进。

评估面向硬件设计和测试的 LLMs

Evaluating LLMs for Hardware Design and Test

Training new engineers in digital design is a challenge, particularly when it
comes to teaching the complex electronic design automation (EDA) tooling used
in this domain. Learners will typically deploy designs in the Verilog and VHDL
hardware description languages to Field Programmable Gate Arrays (FPGAs) from
Altera (Intel) and Xilinx (AMD) via proprietary closed-source toolchains
(Quartus Prime and Vivado, respectively). These tools are complex and difficult
to use -- yet, as they are the tools used in industry, they are an essential
first step in this space. In this work, we examine how recent advances in
artificial intelligence may be leveraged to address aspects of this challenge.
Specifically, we investigate if Large Language Models (LLMs), which have
demonstrated text comprehension and question-answering capabilities, can be
used to generate novice-friendly explanations of compile-time synthesis error
messages from Quartus Prime and Vivado. To perform this study we generate 936
error message explanations using three OpenAI LLMs over 21 different buggy code
samples. These are then graded for relevance and correctness, and we find that
in approximately 71% of cases the LLMs give correct & complete explanations
suitable for novice learners.

通过使用大型语言模型，本研究考察了如何利用人工智能的最新进展，生成适合初学者理解的编译时综合错误消息的解释，以在数字设计中培养新工程师。

利用 LLMs 解释 EDA 综合错误

Explaining EDA synthesis errors with LLMs

Modern hardware design starts with specifications provided in natural
language. These are then translated by hardware engineers into appropriate
Hardware Description Languages (HDLs) such as Verilog before synthesizing
circuit elements. Automating this translation could reduce sources of human
error from the engineering process. But, it is only recently that artificial
intelligence (AI) has demonstrated capabilities for machine-based end-to-end
design translations. Commercially-available instruction-tuned Large Language
Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to
produce code in a variety of programming languages; but studies examining them
for hardware are still lacking. In this work, we thus explore the challenges
faced and opportunities presented when leveraging these recent advances in LLMs
for hardware design. Using a suite of 8 representative benchmarks, we examined
the capabilities and limitations of the state of the art conversational LLMs
when producing Verilog for functional and verification purposes. Given that the
LLMs performed best when used interactively, we then performed a longer fully
conversational case study where a hardware engineer co-designed a novel 8-bit
accumulator-based microprocessor architecture. We sent the benchmarks and
processor to tapeout in a Skywater 130nm shuttle, meaning that these
'Chip-Chats' resulted in what we believe to be the world's first
wholly-AI-written HDL for tapeout.

研究人员探讨了使用最新的 LLMS 技术来进行硬件设计所面临的挑战与机遇，并使用代表性基准套件对其进行了全面的测试和评估，最终实现了全球首个完全由人工智能编写的硬件描述语言。

会话式硬件设计的挑战与机遇

Chip-Chat: Challenges and Opportunities in Conversational Hardware  Design

Innovative Electronic Design Automation (EDA) solutions are important to meet
the design requirements for increasingly complex electronic devices. Verilog, a
hardware description language, is widely used for the design and verification
of digital circuits and is synthesized using specific EDA tools. However,
writing code is a repetitive and time-intensive task. This paper proposes,
primarily, a novel deep learning framework for training a Verilog
autocompletion model and, secondarily, a Verilog dataset of files and snippets
obtained from open-source repositories. The framework involves integrating
models pretrained on general programming language data and finetuning them on a
dataset curated to be similar to a target downstream task. This is validated by
comparing different pretrained models trained on different subsets of the
proposed Verilog dataset using multiple evaluation metrics. These experiments
demonstrate that the proposed framework achieves better BLEU, ROUGE-L, and chrF
scores by 9.5%, 6.7%, and 6.9%, respectively, compared to a model trained from
scratch.

本文提出一种基于深度学习的 Verilog 自动补全模型的训练框架，该框架通过将通用编程语言预训练模型与类似目标下游任务的数据集集成并进行微调来验证，实验结果表明，该框架相比于从头开始训练的模型，具有更好的 BLEU、ROUGE-L 和 chrF 评分。